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S. Alliot et al. (Astron, Leiden University) The communication mechanism in a generic platform (PDF, 1 MB)
M. van den Braak et al. (Delft University of Technology) FPGA implementation of Voice-over IP (PDF, 58.8 KB)
R. Chaves et al. (IST/INESC-ID Portugal, Delft University of Technology) Polymorphic AES Encryption Implementation (PDF, 238.2 KB)
H. Eeckhaut et al. (Ghent University) A Fast Wavelet Entropy Decoder for Scalable Video (PDF, 772.2 KB)
K. Heyrman et al. (Hogeschool Ghent, IMEC, Ghent University) Energy Costs of Transporting Switch Control Bits for a Segmented Bus (PDF, 378.8 KB)
J.Y. Hur et al. (Delft University of Technology) Parallel Merge Sort on a Binary Tree On-Chip Network (PDF, 164.5 KB)
A. Kapoor et al. (University of Twente) A Reconfigurable Tile-Based Architecture to Compute FFT and FIR Functions in the Context of Software-Defined Radio (PDF, 180.4 KB)
H.G. Kerkhoff et al. (MESA+, Lancaster University, LIRRM Montpellier) Determining DfT Hardware by VHDL-AMS Fault Simulation for Biological Micro-Electronic Fluidic Arrays (PDF, 244 KB)
P. de Langen et al. (Delft University of Technology) Multiprocessor Scheduling to Reduce Leakage Power (PDF, 181.9 KB)
B. Li et al. (Philips, Delft University of Technology) TTL inter-task communication implementation on a shared-memory multiprocessor platform (PDF, 0.9 MB)
L. Mhamdi et al. (Delft University of Technology) A Practical Scheduler for High-Speed Packet Switches and Internet Routers (PDF, 0.9 MB)
A.M. Molnos et al. (Delft University of Technology, Philips) Inter-task sharing data and instructions in cache with enabling compositionality in parallel embedded systems (PDF, 227.3 KB)
J. van Muijden et al. (Delft University of Technology) OCM-to-DDR memory controller for VirtexII-Pro FPGAE (PDF, 67.5 KB)
M. Panainte et al. (Delft University of Technology) FPGA-area Allocation for Partial Run-Time Reconfiguration (PDF, 176.6 KB)
G.K. Rauwerda et al. (University of Twente) Implementation of multi-standard wireless communication receivers in a heterogeneous reconfigurable system-on-chip (PDF, 1.4 MB)
R. Romansky (Technical University of Sofia) Stochastic Modeling and Reliability Estimation of the Computer Processing Using Markov Chains (PDF, 151.3)
A. Shahbahrami et al. (Delft University of Technology) Efficient Vectorization of the FIR Filter (PDF, 94.9 KB)
K. Sigdel et al. (Delft University of Technology) Centralized Matchmaking: An Empirical Study (PDF, 199.8 KB)
F. Smailbegovic et al. (Delft University of Technology) Scalable Linear Multiplication Array (PDF, 160 KB)
I. Sourdis et al. (Delft University of Technology, Technical University of Crete) An Evaluation of FPGA-based IDS Pattern Matching Techniques (PDF, 106.4 KB)
D. Verstraeten et al. (Ghent University) Reservoir computing on FPGA using stochastic bitstream neurons (PDF, 135.7 KB)
M. Vidojkovic et al. (Eindhoven University of Technology) Receiver Planning for a Multi-Standard Front-End (PDF, 245 KB)
Q. Zhang et al. (University of Twente, Thales) Low Power Implementation of non Power-of-Two FFTs on Coarse-grain Reconfigurable Architectures (PDF, 311.4 KB)
Y. Zhao et al. (Delft University of Technology) Benchmarking for RSVP Protocol (PDF, 184.8 KB)
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