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M. Ahmadi et al. (Delft University of Technology) Network Processors: Challenges and Trends (PDF, 180 KB)
P. Bertels et al. (Ghent University) Profiling Based Estimation of Communication for System Partitioning (PDF, 185 KB)
R. Chaves et al. (Delft University of Technology, IST/iNESC-ID, Portugal) Reconfigurable Cryptographic Processor (PDF, 148 KB)
J. Chen et al. (Delft University of Technology, Philips) An Advanced Cache Power Model for An Embedded Processor using SLEEP Methodology (PDF, 123 KB)
H. Devos et al. (Ghent University) From loop transformation to hardware generation (PDF, 102 MB)
W. Galjan et al. (Hamburg University of Technology) Distributed Processor Network on a Single Chip (PDF, 296 KB)
C. Galuzzi et al. (Ghent University) Two Algorithms for the Generation of Convex MIMO Instructions (PDF, 288 KB)
K. Hafkemeyer et al. (Delft University of Technology) Design of a process-parameter independent test-structure for reliable tests(PDF, 626 KB)
S. Irobi et al. (Delft University of Technology) On-chip Scatchpad Memory Size Prediction and Allocation for Multiprocess Embedded Applications (PDF, 192 KB)
D. van Kampen et al. (University of Twente) Implementation of a Combined OFDM-Demodulation and WCDMA-Equalization Module (PDF, 202 KB)
K.J. van der Kolk et al. (Delft University of Technology) A Software Tool for 3D Meshing of VLSI Interconnect Structures (PDF, 388 KB)
I. Koryfidis et al. (Delft University of Technology, Philips) Power Aware HW/SW Partitioning for a DVB-H Receiver Module (PDF, 482 KB)
P. de Langen et al. (Delft University of Technology) Reducing Conflict Misses in Caches by Using Application Specific Placement Functions (PDF, 273 KB)
D. Ludovici et al. (Delft University of Technology) Performance Analysis of Scheduling Algorithms in a Reconfigurable Route (PDF, 209 KB)
L. Mhamdi et al. (Delft University of Technology) Multicast Traffic Scheduling Based On High-Speed Crossbar Switches (PDF, 156 KB)
K.N. Mishra et al. (Dhirubhai Ambani Institute of Information & Communication Technology, Gujarat, India, Central Electronics Engineering Research Institute, Pilani, Rajasthan) An Input Pattern Based Area Reduction Technique for Adder Structures in Low Power Applications (PDF, 177 KB)
K.N. Mishra et al. (Dhirubhai Ambani Institute of Information & Communication Technology, Gujarat, India, Central Electronics Engineering Research Institute, Pilani, Rajasthan) A Fast and Power Efficient Bit-Slice Design of a 2-bit Carry-Skip Adder for Automated Layout Applications? (PDF, 414 KB)
M.R. Nami et al. (Delft University of Technology) Autonomic Computing Systems: Issues and Challenges (PDF, 241 KB)
S. Raaijmakers et al. (Delft University of Technology) Run-time Placemnt and Routing of Hardware on the Virtex 2 Pro (PDF, 135 KB)
G.I. Radulov et al. (Eindhoven University of Technology) A Binary-To-Thermometer Decoder With redundant switching sequences (PDF, 474 KB)
A. Shahbahrami et al. (Delft University of Technology) Performance Impact of Misaligned Accesses in SIMD Extensions (PDF, 118 KB)
Z. Sheng et al. (Delft University of Technology) Iterative solution method based on Hierachically Semi-Separable representation (PDF, 303 KB)
C. Strydis et al. (Delft University of Technology) A New Digital Architecture For Reliable, Ultra-Low-Power Systems (PDF, 267 KB)
Y. Yankova et al. (Delft University of Technology) HLL-to-HDL Generation: Results and Challenges (PDF, 242 KB)
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