Programming models and performance evaluation of tile-based architectures (DES.6397)

Research
Powerful embedded processors form the core of many modern consumer electronics (CE) devices. They perform the various signal processing tasks required for audio, video, and transmission handling. Often these processor cores consist of DSPs (Digital Signal Processors) or custom designed VLSI cores. There are a number of problems industry is facing that need attention. A major problem with CE devices is that, due to the increased density in VLSI chips, design and layout of electronic circuits containing various processing components is taking too much time with respect to the ever shortening time-to-market demands of manufacturers of CE devices. Inferior programming methodologies that are currently used for CE devices are making the problem even worse. Application programming is still done by writing hand tuned sequential code in languages like C or even in assembler. Consequently, software design time is high and portability is low, thus increasing time-to-market. A major scientific challenge (with high industrial impact) therefore is how to develop an architecture and programming methodology that reduces the total system development time. The SPACECAKE architecture designed by Philips [28] addresses the architectural part of this problem. It is based on the idea of tiles. A tile is a heterogeneous multiprocessor with a shared memory architecture. A SPACECAKE system consists of a regular structure of tiles. An open problem, however, is how to develop efficient applications for these types of architectures. Programming a SpaceCake system intrinsically means the use of parallelism. In the SCALP project, we will investigate whether a suitable and effective parallel programming paradigm can be defined that is scalable, portable, and predictable. We will base our parallel programming model on SP (series-parallel) graphs, which offer significant advantages with regard to the ease of programming, portability, and performance predictability. We will explore whether SP design patterns can be defined for a relevant set of current and future CE-applications. These SP design patterns will be embedded in an SP programming environment that also provides accurate, low cost estimations on the performance of the design patterns.

Utilization
Philips has identified several application areas where SPACECAKE chips can initially be deployed. The most promising applications are media processing and gaming. Traditionally media processing has been very much a stream oriented discipline, but this is rapidly changing. For example, new video compression schemes require fast random access to arbitrary locations in a fairly large pool of frame buffers; SPACECAKE is well suited to this kind of memory access patterns and it extends easily to HD (high-definition) picture formats. Video compression (and decompression) is important in the "connected home", where media devices are all hooked up to a wireless home network with limited (and therefore precious) bandwidth. Many of these applications require extraordinary compute power (by today's standards). They also require programming paradigms that are a good match with the application domain on the one hand, while allowing an efficient mapping to SPACECAKE on the other hand. The challenge is to provide a range of design patterns that address the various aspects of a modern CE system, including user interface design (graphics), overall system control (event driven, sensitive to latency), pixel crunching (DSP filters with high computational efficiency), and others.ions o Re-use of functional components (both software and hardware) has a very high priority in the industry because of the associated cost savings and improved time to market when applied wisely. Reduced time to market also results from accurate and to-the-point performance estimations because it quickly points system builders to their bottlenecks. From experience we know that even not too complex systems often require disproportional amounts of time to analyze and debug, resulting in late (and consequently canceled) products. Tools that give high-level hints at the problem (preferably at early stages of the esign) are indispensable in such cases.

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