A monolithic process for stacking electronic circuits (DMF.6617)

Future semiconductor world depends on breakthrough in technology. The continuous downscaling of the minimal dimensions of ICs is slowing down, either due to physical limitations or to the high financial risks involved in sub-10 nm IC factories. One of the limitations is that existing ICs are built using active devices within a single layer of Si. Additional layers above are used just for wiring or insulation.
This project will break-through the problems of the conventional 2 dimensional ICs. We will explore a new technology to fabricate multiple layers of high quality silicon atop each other enabling us to integrate complete microelectronic systems in 3 dimensions. This opens new ways to increase the integration density and thus to achieve compactness of overall system with available IC processing technology. Owing to the shorter and denser interconnect paths between the devices, speed of integrated circuits will increase. Moreover, integration of other microelectronics systems, e.g., sensors, right above the circuit will increase the functionalities of the ICs.

The principle of the technology we propose in this project has been
successfully validated in previous STW and FOM projects and is based on the local recrystallization of amorphous silicon film using a high power ultra-violet (excimer) laser. By careful manipulation of the solidification process, high-quality single-crystalline silicon islands can successfully be formed at a predetermined position where electronic circuits can be made. In this project we will extend this technology to 3D IC applications. This implies considerable scientific challenges related to understanding crystal growth mechanisms, controlling the microstructure of Si and the dissipation of massively generated heat from ICs and formation of high-quality thin gate oxide at low-temperature.

Utilisation

The novel 3D IC technology with direct, monolithic, formation of multi Si layers is very attractive for stacking many different circuit blocks atop each other and connecting them, i.e., 3D system-on-chip (SoC). One very interesting application for such system will be a high-speed low-power micro processor unit (MPU). A CPU core with asynchronous clock and memory devices (SRAM, DRAM and FeRAM) are stacked atop each other and connected with metal interconnections. Additional integration of optical interconnect will further increase bus speed. A commercial application of such an MPU can be found in the chips embedded in smart ID card, where considerable intelligent is needed. The technology would open the way for new medical applications. By adding an optical image sensor array on top of the 3D ICs, one could realize a very compact high-resolution intelligent image sensor chip. This chip could be implanted in the eyes as an artificial retina. The social relevance of this application is very high, as it could restore effectively the vision of patients afflicted with retinal degenerative diseases.
A primary user of this project will be SEIKO-EPSON, who is a world leader in producing low-power MPUs as well as the small LCDs. The company puts its efforts into an ultra low-power portable personal information system. When all technical problems are solved, SEIKO-EPSON will demonstrate such MPU as a prototype. Another primary user is ASML, who is a world leader in the manufacturing of photolithography steppers for ICs. In this project, ASML will support the stepper. The knowledge about front-to-backside alignment will be transferred to ASML. This will expand their business towards stepper for MEMs and LCDs and hence bring benefits to Dutch society and the world. Other users of the project are DALSA and ASM International.